1. Field of the Invention
The present disclosure relates to a method for manufacturing electronic circuits integrated on a semiconductor substrate.
The disclosure further relates to a method for manufacturing semiconductor-integrated electronic circuits comprising:
depositing an auxiliary layer on a substrate;
depositing a layer of screening material on said auxiliary layer;
selectively removing said layer of screening material to provide a first opening in said layer of screening material and expose an area of said auxiliary layer.
In particular, though not limited to, the disclosure relates to a method for defining circuit structures of submicron size, wherein the distance between two or more of them is smaller than the distance provided by a conventional photolithographic process and the following description refers to this field of application for convenience of explanation only.
2. Description of the Related Art
As it is well known, one of the basic technological steps for manufacturing integrated circuits is that of transferring some geometries defined by a photosensitive layer (photoresist) on one or more underlying layers: this process is generally called etching step of the layer to be defined.
It is also known how microelectronics has been subjected for years to a general trend providing a continuous size reduction of the various circuit structures forming the integrated circuit. As the size in the photosensitive layers is critical, the different layer etching step has to reproduce sizes without distortions, i.e., the underlying material has to be etched only along a direction being perpendicular to the substrate.
With reference in particular to FIGS. 1 and 2, a portion of a semiconductor electronic circuit is shown, comprising a semiconductor substrate 1 on which a layer 2 of a material to be defined is formed. A layer 3 of photosensitive material is deposited on the layer 2 of material to be defined, and is then selectively removed by using a conventional photolithographic technique so as to expose the areas of the layer 2 to be defined etched. An anisotropic etching is used for the purpose, wherein the wafer in which the electronic device has to be integrated is subjected to a flow of plasma (low-pressure ionized gas). A complex chemio-physical process allows to obtain a process where the lengthwise etching component is absolutely predominating over the transversal T one.
Some methods have been studied to obtain circuit structures being smaller than those obtained through a photolithographic process.
A first prior art solution for obtaining circuit structures in the substrate whose cross-dimension after the etching step is different from that of the photosensitive layer, or anyway allowing to obtain in a layer some circuit structures being smaller than those attainable through a conventional photolithographic process, is illustrated by FIGS. 3 to 5. The method, called Resist trimming, is used for forming a circuit structure, typically of polycrystalline silicon, which has a cross-dimension much smaller than that of the corresponding photosensitive layer.
In particular, a layer 2a of a material to be defined is formed on a semiconductor layer 1a. This is followed by a layer of a photosensitive material being deposited and then selectively removed through conventional photolithographic techniques, as shown in FIG. 3, to produce a strip 3a of width S. A heavily isotropic etching step is then carried out on the strip 3a. This etching step then thins the strip 3a sideways as shown in FIG. 4, so that, after etching, the strip 3a exhibits a smaller width S′ than its original width S. The photosensitive layer strip 3a is then etched anisotropically to define a strip 2a′ in the underlying material layer 2a of width S′.
Although advantageous into many respects, this first solution only allows the size of a lithographed structure to be reduced, but it is not suitable to reduce the distance between two or more structures.
Another solution, employed for providing an opening between two or more adjacent circuit structures rather than for reducing the size of a circuit structure, comprises forming spacers (Spacers formation).
As shown in FIGS. 6 to 11, a layer 2b of a material to be defined and a layer 3b of auxiliary material are formed on a semiconductor substrate 2b. A layer 4b of a photosensitive material is then deposited to permit a selective action by the layer 3b of auxiliary material and provide a first window having dimension L.
A layer 5b is then deposited for defining spacers 6a that are effective to reduce the cross-dimension of the window previously made in the layer 3b, thus reducing the exposed area of the layer 2b to be defined.
The layer 2b is then etched anisotropically to make a second window L′ of a smaller size than the lithographic starting one.
While being advantageous from various points of view, this method for manufacturing spacers narrowing a window previously defined by lithography, has some drawbacks because of the complex circuit architecture made of a succession of depositions and etchings (both isotropic and anisotropic).
In particular, the large number of depositions and etchings greatly worsen the final defect rate of the circuit structure to be realized. In general, particle contaminations deteriorate and heavily worsen the electric characteristics of an integrated circuit. This contamination is partly in the atmosphere, but it is introduced, to a great extent, during each of the process steps for manufacturing the integrated device (masking, depositing, cleaning, etching, etc.).
In addition, the precision with which the width of the spacers can be controlled has strict limits. Actually the spacer dimensions depend on the characteristics of the previous and following steps with respect to the their formation (thickness of the layers used, duration of wet etching, etc.). Accordingly, the accuracy of dimensional control after opening the second window is likely to drop to unsatisfactory levels.
Furthermore, manufacturing costs grow in proportion to the number of operations involved.